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R2S15901SP
Digital Delay IC for "Lip Sync"
REJ03F0151-0100 Rev.1.0 Apr 28, 2005
Description
R2S15901SP is a digital audio delay chip to synchronize the TV video and audio signals.
Features
* * * * CMOS Technology 2-Channel 24-bit Audio signals delay Delay time is controlled by DC voltage (9steps: 1, 7/8, 3/4, 5/8, 1/2, 3/8, 1/4, 1/8 times) 43K bytes RAM up to delay 224ms(@fs = 32kHz) When fs = 48kHz, maximum delay is 149ms. * 2 3-state pins for 9-step configuration * 3.3V signal input available
Recommended Operating Condition
Supply Voltage Range Circuit Current Operation Temperature VDD = 2.5V (typ.) IDD = 1.0mA (typ.) Topr= -20 to 75C
Applications
LCD TV, PDP, DVD Recorder, AV Amplifier
Rev.1.0 Apr 28, 2005 page 1 of 7
R2S15901SP
Block Diagram
BCKI LRI
SDI LRI BCKI
L/R Serial Audio I/F Input
RD RAM I/F WR Di Addr SRAM Do
L/R Serial Audio I/F Output
SDO
Contol
Input/Output Configuration
The schematic diagrams of the input and output circuits of the logic section are shown below:
COU NT 0
COU NT 1
VDD
31K
VDD
H
VDD
31K
L
VSS
Input pin 1, 2, 3
VSS
Input Pin 5, 6
VSS
Output Pin 7
Rev.1.0 Apr 28, 2005 page 2 of 7
R2S15901SP
Pin Configuration
SDI LRI BCKI VSS
1 2 3 4
8 7 6 5
VDD SDO COUNT1 COUNT0
Pin Description
Pin No. 1 Pin Name SDI I I/O Description
* Serial audio data input * The input audio data are fetched at every LRI edge. * * * *
LR clock Audio sample frequency. Low indicates the audio input data SDI and output data SDO are left channel data. High indicates the audio input data SDI and output data SDO are right channel data.
2
LRI
I
3
BCKI
I
* Bit clock input * BCK clock is 64 times as large as LRI and input audio data. * Ground * Delay time control 0 * Delay time control 1 * Delay time control pin. These two inputs are 3-state input pins that may be set high
or low, or left unconnected to generate the third state. With the 3-state condition, 9step delay time may be organized.
4 5 6
VSS COUNT0 COUNT1
-- I
7
SDO
O
* Audio data output * This SDO is the delayed audio data output. * Power supply +2.5V
8
VDD
--
Rev.1.0 Apr 28, 2005 page 3 of 7
R2S15901SP
Function Description
Serial Interface
LRI BCK SDI, SDO
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
The input audio data format is I2S 24-bit 64fs as above with the same as output. Delay Time The R2S15901SP provides 9 steps time delay by using two control pin COUNT0 and COUNT1. The two control pins provide 3-state respectively to generate 9 steps time delay. COUNT0 and COUNT1 may be tied to high, low or left unconnected. Internal comparator circuitry monitor input state to determine the input is high, low or middle state. Internal Pull high and low resistor keep input at VDD/2. The comparator distinguishes terminal voltage level as below.
L
0 0.7 1.0
M
1.5 1.7
H
2.5 Input voltage(V)
Sampling Rate (fs) 192kHz 96kHz 88.2kHz 48kHz 44.1kHz 32kHz (Sampling Counts) Sampling Rate (fs) 192kHz 96kHz 88.2kHz 48kHz 44.1kHz 32kHz (Sampling Counts)
Max COUNT[1:0]=HH 37ms 75ms 81ms 149ms 163ms 224ms (7168) 4/8 COUNT[1:0]=MM 19ms 37ms 41ms 75ms 81ms 112ms (3584)
7/8 COUNT[1:0]=HM 33ms 65ms 71ms 131ms 142ms 196ms (6272) 3/8 COUNT[1:0]=ML 14ms 28ms 30ms 56ms 61ms 84ms (2688)
6/8 COUNT[1:0]=HL 28ms 56ms 61ms 112ms 122ms 168ms (5376) 2/8 COUNT[1:0]=LH 9ms 19ms 20ms 37ms 41ms 56ms (1792)
5/8 COUNT[1:0]=MH 23ms 47ms 51ms 93ms 102ms 140ms (4480) 1/8 COUNT[1:0]=LM 5ms 9ms 10ms 19ms 20ms 28ms (896) 0 COUNT[1:0]=LL 0ms 0ms 0ms 0ms 0ms 0ms (0)
The delay time is evaluated by the following formula: Delay Time = (1/fs) x (sampling counts + 1) sec
Rev.1.0 Apr 28, 2005 page 4 of 7
R2S15901SP
Mode Change
The R2S15901SP samples COUNT0 and COUNT1 pins while LRI is low by BCKI. When COUNT0 and COUNT1 are sampled and changed, they are detected at low interval of LRI. The delay counts start from the following falling edge of LRI with SDO to be delayed by sample counts + 1. The SDO output is muted before the first new delay data being issued, when the new mode is recognized. An internal POR(Power On Reset) circuitry is to setup the initial mode right after power applied.
Digital Audio Delay
COUNT0, 1
Mode switch detect Sample counts + 1
LRI
BCKI
SDO
23 22 21 20
23 22 21 20
23 22 21 20
SDI
23 22 21 20
Mode change timing
Absolute Maximum Ratings
(Unless otherwise stated, VDD = 2.5V, VSS = 0V, Ta = 25C)
Parameter Power supply voltage Input pin voltage Power dissipation Operating temperature Storage temperature VDD VI PD Topr Tstg Symbol Ratings -0.3 to +2.75 -0.3 to 3.6 100 -20 to +75 -40 to +125 Unit V V mW C C
Rev.1.0 Apr 28, 2005 page 5 of 7
R2S15901SP
Electrical Characteristics
(Unless otherwise stated, VDD = 2.5V, VSS = 0V, Ta = 25C)
Parameter Operating VDD voltage Operating current High level input voltage Low level input voltage Output high voltage Output low voltage Input high current Input high current with 31k pull down Input low current Input low current with 31 k pull up Input capacitance Input rise/fall transition time Symbol VDD IDD VIH VIL VOH VOL IIH IIH(PD) IIL IIL(PU) CIN Tr/Tf Min. 2.25 -- 1.7 -- 1.85 0 -10 40 -10 -160 -- -- -80 10 -- Typ. 2.5 1 Max. 2.75 -- 3.3 0.7 VDD 0.4 10 160 10 -40 -- 100 Unit V mA V V V V A A A A pF nS Test Condition BCKI: 13MHz SDO: CL=25pF LRI, SDI, BCKI LRI, SDI, BCKI IOH = -2mA IOL = 2mA VIN = VDD VIN = VDD COUNT0, COUNT1 VIN = VSS VIN = VSS COUNT0, COUNT1
-- -- -- -- --
80
Serial Audio Timing
Serial Audio Input Timing Parameters
Parameter BCKI frequency BCKI period BCKI to LRI time LRI to BCKI time Data Setup time Data Hold time Data output delay L pulse width H pulse width Symbol fBCK tSIL tSIH tSLI tLSI tDS tDH tDOD Min. -- 35 35 15 15 15 15 -- Typ. -- -- -- -- -- -- -- Max. 13 -- -- -- -- -- 15 Unit MHz ns ns ns ns ns ns ns SDO: CL = 25pF Test Condition
LRI
tSIH tSIL tSLI tLSI
BCKI
tDS tDH
SDI
SDO
tDOD
Rev.1.0 Apr 28, 2005 page 6 of 7
R2S15901SP
Package Dimensions
8-Pin, SOP Package Body Size : 150mil Pin pitch : 1.27mm
Rev.1.0 Apr 28, 2005 page 7 of 7
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